RFCLK=RISING_EDGE, DUAL=QUAD_PROTOCOL, PRFTCH_DIS=ENABLE, MODE3=SCK_LOW, FBCLK=INTERNAL_CLOCK
SPIFI control register
| TIMEOUT | This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again. |
| CSHIGH | This field controls the minimum CS high time, expressed as a number of serial clock periods minus one. |
| RESERVED | Reserved. |
| D_PRFTCH_DIS | This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses. |
| INTEN | If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details. |
| MODE3 | SPI Mode 3 select. 0 (SCK_LOW): SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH. 1 (SCK_HIGH): SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame. |
| RESERVED | Reserved. |
| PRFTCH_DIS | Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines. 0 (ENABLE): Enable. Cache prefetching enabled. 1 (DISABLE): Disable. Disables prefetching of cache lines. |
| DUAL | Select dual protocol. 0 (QUAD_PROTOCOL): Quad protocol. This protocol uses IO3:0. 1 (DUAL_PROTOCOL): Dual protocol. This protocol uses IO1:0. |
| RFCLK | Select active clock edge for input data. 0 (RISING_EDGE): Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation. 1 (FALLING_EDGE): Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame. |
| FBCLK | Feedback clock select. 0 (INTERNAL_CLOCK): Internal clock. The SPIFI samples read data using an internal clock. 1 (FEEDBACK_CLOCK): Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame. |
| DMAEN | A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode. |